1. Field of the Invention
The present invention generally relates to a Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). In particular, the invention relates to non-planar MOSFETs (i.e. FinFET or tri-gate transistors) with asymmetric recessed source and drains having reduced source-side extrinsic resistance and drain-side fringing capacitance and methods of making the same. The methods include using a fin-last, replacement gate process to form the non-planar MOSFETs and, in particular, employ a retrograde metal lift-off process to form the asymmetric source/drain recesses.
2. Description of Related Art
Extrinsic resistance (herein “Rext”) and fringing capacitances reduce the performance of FETs, including finFET and tri-gate transistors. In particular high capacitance in the drain side of a transistor and high resistance on the source side reduce device performance. Methods of fabricating and structures that reduce resistance and capacitance are desired.
However, techniques associated with reducing source/drain resistance to improve drive current often simultaneously increase the gate to drain capacitance, thereby increasing circuit delay. Similarly, techniques associated with reducing gate to source/drain capacitance often simultaneously increase source resistance, thereby degrading drive current. Thus, there is often a trade-off between decreasing source resistance to improve drive current and decreasing gate to drain capacitance to minimize circuit delay.